DVI's digital video transmission format is based on PanelLink, a serial format developed by Silicon Image that utilizes a high-speed serial link called transition minimized differential signaling (TMDS). Like modern analog VGA connectors, the DVI connector includes pins for the display data channel (DDC). A newer version of DDC called DDC2 allows the graphics adapter to read the monitor's extended display identification data (EDID). If a display supports both analog and digital signals in one DVI-I input, each input method can host a distinct EDID. Since the DDC can only support one EDID, there can be a problem if both the digital and analog inputs in the DVI-I port detect activity. It is up to the display to choose which EDID to send.
When a source and display are connected, the source first queries the display's capabilities by reading the monitor EDID block over an I²C link. The EDID block contains the display's identification, color characteristics (such as gamma level), and table of supported video modes. The table can designate a preferred mode or native resolution. Each mode is a set of CRT timing values that define the duration and frequency of the horizontal/vertical sync, the positioning of the active display area, the horizontal resolution, vertical resolution, and refresh rate.
For backward compatibility with displays using analog VGA signals, some of the contacts in the DVI connector carry the analog VGA signals. To ensure a basic level of interoperability, DVI compliant devices are required to support one baseline video mode, "low pixel format" (640×480 at 60 Hz). Digitally encoded video pixel data is transported using multiple TMDS links. At the electrical level, these links are highly resistant to electrical noise and other forms of analog distortion.
A single-link DVI connection consists of four TMDS links; each link transmits data from the source to the device over one twisted wire pair. Three of the links represent the RGB components – red, green, and blue – of the video signal for a total of 24 bits per pixel. The fourth link carries the pixel clock. The binary data is encoded using 8b10b encoding. DVI does not use packetization, but rather transmits the pixel data as if it were a rasterized analog video signal. As such, the complete frame is drawn during each vertical refresh period. The full active area of each frame is always transmitted without compression. Video modes typically use horizontal and vertical refresh timings that are compatible with CRT displays, though this is not a requirement. In single-link mode, the maximum pixel clock frequency is 165 MHz that supports a maximum resolution of 2.75 megapixels (including blanking interval) at 60 Hz refresh. For practical purposes, this allows a maximum 16:10 screen resolution of 1920 × 1200 at 60 Hz (1915 × 1436 at a 4:3 ratio).[citation needed]
To support higher-resolution display devices, the DVI specification contains a provision for dual link. Dual-link DVI doubles the number of TMDS pairs, effectively doubling the video bandwidth. As a result, higher resolutions up to 2560 × 1600 are supported at 60 Hz.
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